Title: x86assembly - ch2 - processor architecture
Tags: ch2

The central processor unit (CPU), where calculations and logical operations take place, contains a limited number of storage locations named registers, a high-frequency clock, a control unit, and an arithmetic logic unit.
Topic: ch2

Q: In the CPU, the [...]synchronizes the internal operations with other system components.
A: clock

Q: In the CPU, the [...] [...] coordinates the sequencing of steps involved in executing machine instructions.
A: control; unit (CU)
Topic: ch2

Q: In the CPU, the [...] [...] [...] performs arithmetic operations such as addition and subtraction and logical operations such as AND, OR, and NOT.
A: arithmetic; logic; unit (ALU)
Topic: cpu

The CPU is attached to the rest of the computer via pins in the CPU socket of the computer's motherboard. Most pins connect to the data bus, the control bus, and the address bus.
The memory storage unit is where instructions and data are held while the computer is running. It recieves requests for data from the CPU and transfers data from random access memory (RAM) to the CPU, and transfers data from the CPU into random access memory.
Because all processing of data takes place within the CPU, programs residing in memory must be copied into the CPU before they can execute. They can be copied 1 instruction at a time, or in groups of instructions.
Topic: cpu connection

Q: A [...] is a group of [...] [...] that transfer data from one part of the computer to another.
A: bus; parallel; wires
Topic: cpu architecture

The data bus transfers instructions and data between the CPU and memory.
The I/O bus transfers data between the CPU and system IO devices.
The control bus uses binary signals to synchronize actions of all devices attached to the system bus.
The address bus holds the addresses of instructions and data when the currently executing instruction transfers data between the CPU and memory.
Topic: bus

Every operation involving the CPU and system bus is synchronized by an internal clock pulsing at a constant rate.
The basic unit of time for machine instructions is a machine cycle, a.k.a. a clock cycle.
The length of a clock cycle is the time required for one complete clock pulse.
Topic: clock

The duration of a clock cycle is calculated as the reciprocal of the clock's speed, which is measured in oscillations per second.
A clock that oscillates 1 billion times per second (1 GHz ) produces a clock cycle with a duration of one billionth of 1 second, or 1 nanosecond.
Topic: clock

Every machine instruction requires at least one clock cycle to execute, and some require more than 50 clocks. Instructions requiring memory access may have empty clock cycles called wait states because of the differences between the speeds of the CPU, the system bus, and the memory circuits.
Topic: clock

Every machine instruction has a pre-defined sequence of steps to execute, called the instruction execution cycle. For example:
1. Fetch the instruction from the instruction queue and increment the instruction pointer.
2. Decode the instruction by looking at its binary bit pattern
3. If the binary bit pattern indicates that the instruction has operands, fetch the operands from registers and memory. Perform address calculations if necessary.
4. Execute the instruction, using any fetched operands, and update status flags like Zero, Carry, and Overflow.
5. If an output operand was part of the instruction, store the result of the execution and its operand.
Topic: instructions

Q: To summarize the instruction execution cycle, there are three basic steps:
1. [...]
2. [...]
3. [...]
A: Fetch; Decode; Execute
Topic: instruction execution cycle

To read program instructions from memory, the CPU places an address on the address bus.
Then, a memory controller places the requested code on the data bus, making the code available in the code cache.
The instruction pointer's value determines which instruction will be executed next.
The instruction is analyzed by the instruction decoder, causing the appropriate digital signals to be sent to the control unit, which coordinates the Arithmetic Logic Unit and floating-point unit.
The control bus carries signals that use the system clock to coordinate the transfer of data between the different CPU components.
Topic: instruction execution cycle

Computers read memory more slowly than they access internal registers, because accessing memory (RAM) involves four separate steps.
1. Place the address of the value you want to read on the address bus.
2. Assert (change the value of) the processor's RD (read) pin.
3. Wait one clock cycle for the memory chips to respond.
4. Copy the data from the data bus to the destination operand.
Topic: read from memory

CPUs reduce memory bottleneck by storing the most recently used instructions and data in high-speed memory called cache.
When a program begins to execute, it can also look ahead and load the next X instructions into cache.
When the processor is able to find its data in cache memory, it's called a cache hit.
When a CPU tries to find something in cache and it's not there, it is called a cache miss.
Topic: memory

The x86 has two types of cache memory.
Level-1 cache, or primary cache, is stored right on the CPU.
Level-2 cache, or secondary cache, is slightly slower, and is attached to the CPU by a high-speed data bus.
Topic: cache

Cache memory is faster than conventional RAM because it's constructed from a more expensive chip called static RAM. Unlike conventional dynamic RAM, static RAM doesn't have to be refreshed constantly to keep its contents.
Topic: cache

Q: Before a program can run, it must be loaded into memory by a [...] [...].
After loading, the operating system must point the CPU to the program's entry point, which is the [...] at which the program is to begin execution.
A: program; loader; address
Topic: program loading

These are the steps by which a program loads:
1. The OS searches for the filename in the disk. If it can't find it there, it searches predetermined paths. If it can't be found, an error message is issued.
2. If the program is found, the OS retrieves basic information from the disk such as the file size and physical location on the disk drive.
3. The OS determines the next available location in RAM and loads the program into memory. It allocates a block of memory to the program and enters info about the programs size and location into a table called a descriptor table. The OS may also adjust values of pointers within the program so they contain addresses of program data.
4. The OS begins execution of the programs first machine instruction (its entry point). As soon as it begins running, the program is called a process. The OS assigns the process an identification number called a process ID.
5. The OS tracks the execution of the process and responds to requests for system resources, such as memory, disk files, and I/O devices.
6. When the process ends, it is removed from memory.
Topic: program loading

x86 processors have three primary modes of operation; protected mode, real-address mode, and system management mode. A sub-mode, named virtual-8086, is a special case of protected mode.
Topic: modes of operation

Q: [...] mode is the native state of the processor, where all instructions and features are available. Programs are given memory areas named [...], and the processor prevents programs from referencing memory outside their assigned [...].
A: Protected; segments; segments
Topic: modes of operation

Virtual-8086 mode is a type of protected mode where the processor can directly execute real-address mode software such as MS-DOS programs in a safe environment. If a program crashes or attempts to write data into the system memory area, it will not affect concurrently running programs. A modern OS can execute multiple separate virtual-8086 sessions at the same time.
Topic: modes

Q: [...]-[...] mode implements the programming environment of an early Intel processor with some extra features, such as switching into other modes. It is useful if a program requires direct access to system memory and hardware devices.
A: Real; address
Extra: Link to digital antiquarian article:
url: https://www.filfre.net/2017/04/the-640-k-barrier/
Topic: modes

Q: [...] [...] mode ([...]) provides an OS with a mechanism for implementing functions such as power management and system security. It is typically used by computer manufacturers customizing the processor for a particular system setup.
A: System; management; SMM
Topic: modes

In 32-bit protected mode, a task or program can address a linear address space of up to 4 gigabytes.
Beginning with the P6 processor, a technique called extended physical addressing allows a total of 64 Gigabytes of physical memory to be addressed.
Real-address mode programs can only address a 1 megabyte range.
If the processor is in virtual-8086 mode, each program has its own 1 megabyte memory area.
Extra: Link to cool article about the 640k problem on digital antiquarian
url: https://www.filfre.net/2017/04/the-640-k-barrier/
Topic: execution environment

Registers are high-speed storage locations directly inside the CPU, designed to be accessed at a much higher speed than conventional memory.
There are eight general-purpose registers, six segment registers, one processor status flags register, and one instruction pointer.
Topic: registers

The general purpose registers are primarily used for arithmetic and data movement.
There are multiple ways to reference and access a given general purpose register. For example, the A register can be accessed in the following ways:
- EAX - access the whole 32 bits
- AX - access the lower 16 bits
- AH - access the upper 8 bits of AX
- AL - access the lower 8 bits of AX
The same overlapping relationship exists for EBX, ECX, and EDX.
Topic: general purpose registers

Four of the general purposes registers do not have the "H" and "L" 8 bit access registers. They just have the 32-bit and 16-bit names.
Those registers are
ESI for 32 bit, with SI being the 16 bit.
EDI for 32 bit, with DI being the 16 bit.
EBP for 32 bit, with BP being the 16 bit.
ESP for 32 bit, with SP being the 16 bit.
Topic: general purpose registers

Some general purpose registers have specialized uses.
- EAX is automatically used by multiplcation and division instructions. It is often called the extended accumulator register.
- The CPU automatically uses ECX as a loop counter.
- ESP addresses data on the stack. It is rarely used for ordinary arithmetic or data transfer. It is called the extended stack pointer register.
- ESI and EDI are used by high-speed memory transfer instructions. They are sometimes called the extended source index and extended destination index registers.
- EBP is used by high-level languages to reference function parameters and local variables on the stack. It shouldn't be used for ordinary arithmetic or data transfer. It is often called the extended frame pointer register.
Topic: general purpose registers

In real-address mode, 16 bit segment registers indicate base addresses of preassigned memory areas named segments.
In protected mode, segment registers hold pointers to segment descriptor tables.
Some segments hold program instructions (code), others hold variables (data), and another segment named the stack segment holds local function variables and function parameters.
Topic: segment registers

The EIP, or instruction pointer, contains the address of the next instruction to be executed.
Machine instructions can manipulate EIP and cause the program to branch to a new location.
Extra: Link works
url: https://wiki.skullsecurity.org/index.php?title=Registers#eip
Topic: pointer

Q: The [...] register consists of individual binary bits that control the operation of the CPU or reflect the outcome of some operation.
A flag is set if it equals 1, it is clear or reset if it equals zero.
A: EFLAGS
Topic: flags

Control flags control CPU operation. They can cause the CPU to break after every instruction executes, interrupt when arithmetic overflow is detected, enter virtual-8086 mode, and enter protected mode.
Programs might set Control flag bits in EFLAGS such as the Direction and Interrupt flags, for example.
Topic: flags

The status flags in EFLAGS reflect the outcomes of arithmetic and logical operations performed by the CPU.
- The Carry Flag (CF) is set when the result of an unsigned arithmetic operation is too large to fit in the destination.
- The Overflow flag (OF) is set when the result of a signed arithmetic operation is too large or too small to fit into the destination.
- The Sign flag (SF) is set when the result of an arithmetic or logical operation generates a negative result.
- The Zero Flag (ZF) is set when the result of an arithmetic or logical operation generates a result of zero.
- The Auxiliary Carry flag (AC) is set when an arithmetic operation causes a carry from bit 3 to bit 4 in an 8-bit operand.
- The Parity Flag (PF) is set if the least-signficant byte in the result contains an even number of 1 bits. Otherwise, it is clear. It is used for error checking when there is a possibility that data might be altered or corrupted.
Topic: flags

There are 8 64 bit MMX registers which support special instructions called Single-Instruction, Multiple-Data (SIMD).
MMX instructions operate in parallel on the data values contained in the MMX registers. While they appear to be separate registers, the MMX register names are aliases to the same registers used by the floating-point unit.
Extra: Link works
url: https://en.m.wikibooks.org/wiki/X86_Assembly/MMX
Topic: registers

Q: The x86 also has eight [...]-bit registers called [...] registers. They are used by streaming [...] extensions to the instruction set.
A: 128; XMM; SIMD
Extra: SIMD = Single-Instruction, Multiple-Data
Link works
url: https://en.m.wikipedia.org/wiki/Streaming_SIMD_Extensions#Registers
Topic: registers

Q: The [...]-[...] unit (FPU) performs high-speed floating-point arithmetic. This used to be on a separate coprocessor chip, but it is now integrated into the main processor chip.
The FPU uses eight [...]-bit floating-point data registers which are inside the FPU, named ST(0), ST(1), ST(2), ST(3), ST(4), ST(5), ST(6), and ST(7).
A: floating; point; 80
Extra: The FPU also uses two 48-bit pointer registers named the FPU instruction pointer and FPU data pointer.
It also uses 3 16-bit control registers named the Tag register, Control register, and Status register.
Link works.
url: https://en.m.wikibooks.org/wiki/X86_Assembly/Floating_Point
Topic: fpu

Q: 64 bit x86-64 processors are backwards compatible with the x86 instruction set.
Addresses are 64 bits long but with current chips, only the lowest [...] bits are used.
It can use 64-bit general purpose registers so instructions can have 64-bit operands.
It has [...] more general-purpose registers than the x86.
It uses a [...]-bit physical address space which supports up to 256 terabytes of ram.
A: 48; 8; 48
Topic: 64 bit x86

Q: The x86-64 has two new modes.
[...] mode allows 32 bit applications to run without being recompiled.
[...]-[...] mode runs applications that use the 64-bit linear address space. It enables 64-bit instruction operands.
A: Compatibility; 64; bit
Topic: 64 bit x86

The biggest difference between 64-bit mode on 64 bit processors and 32 bit processors are:
- Sixteen 64-bit general purpose registers instead of eight 32-bit general purpose registers.
- Eight 80-bit floating point registers.
- A 64-bit status flags register named RFLAGS (only the lower 32 bits are used though)
- A 64-bit instruction pointer named RIP
- Eight 64-bit MMX registers
- Sixteen 128-bit XMM registers instead of eight for 32 bit mode.
Topic: 64 bit x86

In 64 bit mode, the default operand size is 32 bits unless you add the REX (register extension) prefix to each instruction, which allows for 64-bit operands.
Besides the same registers from 32-bit mode, there are an additional 8 numbered registers named R8 through R15.
Topic: x86 64 bit

Q: In 64-bit mode, the 32-bit [...] register is replaced by a 64-bit [...] register but the registers share the same lower 32 bits and the upper 32 bits of [...] are not used. The status flags are also the same between them.
A: EFLAGS; RFLAGS; RFLAGS
Topic: x86 64 bit

There are several basic types of memory in intel-based systems.
- ROM is Read-Only-Memory and is permanently burned into a chip and cannot be erased.
- EPROM is Erasable Programmable Read-only memory and can be erased slowly with ultravoilet light and reprogrammed.
- DRAM, or main memory, is where programs and data are kept while a program is running. It must be refreshed every millisecond to avoid losing its contents.
- SRAM is primarily used for expensive, high-speed cache memory. It does not have to be refreshed.
- VRAM holds video data. It is dual-ported so one port can continuously refresh the display while another port writes data to the display.
- CMOS RAM on the motherboard stores system setup information. It is refreshed by a battery and its contents are retained even when power is off.
Topic: memory